As the number of input and output (I/O) signals increases there will be a point where conventional packages, including multilevel ceramic (MLC) packages can not provide enough output pads within the footprint of the die or especially wire paths on the packaging substrate under the die footprint.
I/Os can be distributed on a die in two ways, along the periphery of the die in one or several rings of pads or throughout the surface area of the die in an array of pads. Dies using pad periphery layouts encounter space limitations at lower counts than pad array layouts. Given a 5 mm die with 100 micron pads on 200 micron centers only about 100 peripheral pads can be laid out but over 600 array pads. For a 20 mm die the number of pads are about 600 and 10,000 respectively. Moving from peripheral pad layouts to array pad layouts forestalls this problem somewhat. However pad array layouts require more complex and costly fabrication techniques invariably involving solder ball interconnection. Further as semiconductor technology results in further density increases resulting in decreasing die size and increasing I/O count even the pad size and spacing on array pad layouts must decrease. For example, a 10,000 I/O count on a 5 mm die would require pads of 25 micron on 50 micron centers. At such small pad sizes the cost and complexity of interconnect processing are not insignificant.
Wiring density on the surface of the package substrates has lead to the use of multi-level ceramic modules. However layer counts can increase extremely fast and when multi chip modules (MCM) are considered the difficulty of packaging wire density increases even more.
Finally the size and density of the wires or lands on the surface and within the layers of the packaging substrate is limited, such that, problems with resistance, capacitance, and delay issues arise.